Tags	No category tags.
Version	0.3.1
License	Apache License 2.0
Build type	AMENT_CMAKE
Use	RECOMMENDED

Description	ROS 2 package examples demonstrating the use of hardware acceleration.
Checkout URI	https://github.com/ros-acceleration/acceleration_examples.git
VCS Type	git
VCS Version	main
Last Updated	2024-12-13
Dev Status	UNKNOWN
CI status	No Continuous Integration
Released	UNRELEASED
Tags	fpga gpu hardware-acceleration ros2
Contributing	Help Wanted (0) Good First Issues (0) Pull Requests to Review (0)

A trivial double vector-add ROS 2 publisher that adds two inputs to a vector in a loop and attempts to publish them on the go at 10 Hz. Vector add operations are offloaded into to the FPGA. This example builds on top of "doublevadd_publisher" which is only able to publish at 2 Hz on the quad-core Cortex-A53 Application Processing Units (APUs) of the Zynq Ultrascale+ (ZU+) SoC. The offloading operation into the FPGA (or to the Programmable Logic (PL)) uses code "as is" and doesn't exploit any parallelism nor optimizes the computation flows. Correspondingly, the publisher does not improve its performance when compared to its CPU baseline. In fact the performance degrades and its publishing rate lowers from from 2 Hz, up to 1.5 Hz. See "accelerated_doublevadd_publisher" for a version that optimizes the computation flow. See "faster_doublevadd_publisher" for another version that besides the computation flow, also exploits parallelism to meet the targeted rate (10 Hz).

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• Víctor Mayoral Vilches

• Víctor Mayoral Vilches